Join Dr Li Chen and Christopher Elash, from the University of Saskatchewan, to explore how their STARRLab team is taking RISC-V from the lab to orbit, with a fully taped-out, space-ready ASIC based on OpenHW Foundation’s CORE-V-MCU.
You’ll learn how USask implemented transistor-level hardening techniques, built a custom devkit, and are preparing StarRISC for launch – paving the way for future industry ready, rad-hard chips.

StarRISC: Rad-hard RISC-V for outer space!